This invention relates to non-overlapping two-phase, signal generators useful in integrated circuits for very high frequency applications (i.e. at frequencies lying close to the upper limit allowed by the integration technology), and particularly to such generators in combination with voltage multiplier circuits, especially in CMOS-type memory devices.
There are many applications which require the availability of non-overlapping two-phase digital signals (i.e. signals having a near-square waveform and a "non-overlap" characteristic such that the signals have equal frequency and are substantially in phase opposition).
A perfectly square waveform (with perfectly vertical edges) is not obtainable in a real physical circuit. However, to attain high operating frequencies in a digital circuit, steep edges of the waveform are desirable.
Two iso-frequential signals .PHI.1 and .PHI.2, substantially in phase opposition and having near-square waveforms, can be obtained conventionally using a loop oscillator consisting of an odd number of cascaded inverters. If the outputs from two inverters adjacent to each other are taken to drive the set (S) and reset (R) inputs of a set-reset type of flip-flop such that the output signals are both zero (inactive) when the set and reset inputs are both one (active), then the output signals from the flip-flop (Q,Q ) will fill the above requirements. In tact, each output, Q and Q , can only switch from a logic level of 0 to a logic level of 1 after the other output has attained a logic level of 0.
Alternatively, the output of just one of the loop inverters may be taken and the flip-flop driven with that signal and its complement (obtained therefrom by means of an inverter).
In either case, the oscillation period, and hence the repetition period of the generated signals, will be equal to the sum total of the switch times of the oscillator inverters.
Where the phase "non-overlap" time is to be increased, an even (and normally equal) number of inverters may be connected in each of the two positive feedback paths of the flip-flop. This is conventionally implemented, for example, with two logic gates of the NOR type.
However, where a very high signal frequency is sought, the number of the inverters comprising the loop oscillator should be quite small. In the extreme, a loop formed of as few as three inverters could be used, with each inverter comprising transistors of small dimensions in order to minimize the switch times.
In this case, the switch times for the available signals at the various nodes in the loop, and those required by the logic gates which make up the flip-flop, are not negligible compared to oscillation period (as is the case, instead, with a large number of stages in the loop). The two signals Q and Q would therefore be active for an extremely short time; and as a result, they may be unable to adequately drive the circuit for which they have been generated.
A very high signal frequency is desirable where the non-overlapping phase signals are used, as mentioned, to drive a voltage multiplier device which is to afford high output current capabilities; the deliverable current (for a given capacitor and transistor sizing) being directly proportional to the frequency of the drive signals.
Voltage multiplier circuits are also employed in nonvolatile integrated memories for write and erase functions. Floating-gate memories (such as EPROMs, EEPROMs, or flash EPROMs) normally require voltages well above 5V for programmation of the cells. (Voltage multiplier circuits use charge pumping through capacitors to achieve a voltage which is higher than the supply voltage.)
In the instance of non-overlapping two-phase signals operating at the limits allowed by the integration technology, a very small overlap in the signal active phases, and less-than-true "verticality" of the rising and falling edges, may be acceptable if the active phase times are sufficient.
It is an object of this invention to provide a non-overlapping phase signal generator which exhibits, when compared to prior art generators, improved "non-overlap of phases" at the highest frequencies, without involving any substantial reduction in the active phase times.
A further object of the invention is to ensure proper operation of the non-overlapping phase signal generator at the highest frequencies irrespective of the technology employed for its integration.
These objects are achieved by a signal generator which includes two feedback gates which cross-couple each ring oscillator to the other. That is, in each oscillator, a first node gates a coupling transistor which connects a second node (complementary to the first node) across to drive the first node of the other oscillator.
For example, in FIG. 1, the non-overlapping-phase signal generator comprises first and second loop oscillators (O1 ,O2) including cascaded inverters. Defined in each cascade of inverters are first and second circuit nodes between the inverters. Between the first node (2) of the first oscillator (O1) and the second node (3A) of the second oscillator, there is connected a transistor having a control terminal connected to the first node of the second oscillator. Connected between the first node (2A) of the second oscillator (O2) and the second node (3) of the first oscillator is a transistor having a control terminal connected to the first node of the first oscillator (O1).
According to the innovative teachings set forth herein, there is provided: an integrated circuit for generating non-overlapping complementary clock signals, comprising: first and second mutually matched ring oscillators, each comprising an odd number of inverting digital gates connected in a loop, at least one of the inverting gates of each the oscillator being connected to be driven by a first node of the oscillator and configured to drive a second node of the oscillator in opposition to the first node; a first switch connected to be driven by the first node of the first oscillator, and connected so that the second node of the first oscillator is connected to the first node of the second oscillator when the first transistor is turned on; and a second switch connected to be driven by the first node of the second oscillator, and connected so that the second node of the second oscillator is connected to the first node of the first oscillator when the second transistor is turned on; wherein at least one node of the first oscillator is connected to provide a first clock signal, and the corresponding node of the second oscillator is connected to provide a second clock signal which does not overlap with the first clock signal.
According to the innovative teachings set forth herein, there is also provided: a CMOS integrated circuit for generating non-overlapping complementary clock signals, comprising: first and second mutually matched ring oscillators, each comprising an odd number of inverting digital gates connected in a loop, at least one of the inverting gates of each the oscillator consisting of a simple CMOS inverter which is connected to be driven by a first node of the oscillator and configured to drive a second node of the oscillator in opposition to the first node; at least one first NMOS coupling transistor connected to be driven by the first node of the first oscillator, and connected so that the second node of the first oscillator is connected to the first node of the second oscillator when the first transistor is turned on; and a second NMOS coupling transistor connected to be driven by the first node of the second oscillator, and connected so that the second node of the second oscillator is connected to the first node of the first oscillator when the second transistor is turned on; wherein at least one node of the first oscillator is connected to provide a first clock signal, and the corresponding node of the second oscillator is connected to provide a second clock signal which does not overlap with the first clock signal.
According to the innovative teachings set forth herein, there is also provided: an integrated circuit on-chip high-voltage generator, comprising: a voltage multiplier circuit, including two or more switches connected to be driven by first and second non-overlapping clock signals, and one or more capacitors interconnected with the switches to effect charge pumping; and a clock generation circuit comprising: first and second mutually matched ring oscillators, each comprising an odd number of inverting digital gates connected in a loop, at least one of the inverting gates of each the oscillator being connected to be driven by a first node of the oscillator and configured to drive a second node of the oscillator in opposition to the first node; a first coupling transistor connected to be driven by the first node of the first oscillator, and connected so that the second node of the first oscillator is connected to the first node of the second oscillator when the first transistor is turned on; and a second coupling transistor connected to be driven by the first node of the second oscillator, and connected so that the second node of the second oscillator is connected to the first node of the first oscillator when the second transistor is turned on; wherein at least one node of the first oscillator is connected to provide the first clock signal, and the corresponding node of the second oscillator is connected to provide the second clock signal.
According to the innovative teachings set forth herein, there is also provided: a non-overlapping phase, signal generator circuit comprising: at least first and second loop oscillator circuits with cascaded inverters, each the oscillator circuit having first and second circuit nodes with at least one of the inverters connected therebetween, and at least first and second switch circuit means, each having first and second terminals and a control terminal, the first switch circuit means being connected with its first and second terminals between the first circuit node of the first oscillator circuit and the second circuit node of the second oscillator circuit, the second switch circuit means being connected with its first and second terminals between the second circuit node of the first oscillator circuit and the first circuit node of the second oscillator circuit, the control terminal of the first switch circuit means and the control terminal of the second switch circuit means being respectively coupled to the first circuit node of the second oscillator circuit and the first circuit node of the first oscillator circuit.
According to the innovative teachings set forth herein, there is also provided: a non-overlapping phase, signal generator circuit comprising: at least first and second loop oscillators and at least first and second switch circuit means having control terminals respectively coupled to a first point in the signal path of the second loop oscillator and a first point in the signal path of the first loop oscillator, the second switch means being connected between the first point in the signal path of the second loop oscillator and a second point in the signal path of the first loop oscillator, whereat a signal has a different phase from the phase it has at the first point in the signal path of the first loop oscillator, the first switch means being connected between the first point in the signal path of the first loop oscillator and a second point in the signal path of the second loop oscillator, whereat a signal has a different phase from the phase it has at the first point in the signal path of the second loop oscillator.
The features and advantages of a non-overlapping two-phase signal generator according to the invention will become apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.